Groups

  • This task group is responsible for updating and maintaining current carrying capacity charts as published in IPC-2152.
  • This task group is responsible for developing and maintaining conformance test circuitry for use in IPC-2220 design standards and IPC-6010 performance specifications, as well as generating the appropriate artwork packages for fabrication of the test circuitry.
  • This subcommittee is responsible for land pattern design concepts through the development of IPC-7351 for SMT design rules and land pattern configurations, and IPC-7251 for THT design rules and land pattern configurations.
  • This subcommittee is developing guidelines for the application of industry standards in DFM (design for manufacturing), DFR (design for reliability) DFA (design for assembly), etc. The group has a goal of publishing these guidelines in early 2015.
  • This task group is working jointly with JEDEC and ECIA on J-STD-048, which outlines the standard for announcing product discontinuance throughout the supply chain.
  • This subcommittee is responsible for the maintenance and further development of a suite of standards known as "Offspring" of GenCAM and ODB++ formats. It is documented in the standard series IPC-258X. The series consists of eight standards ranging from IPC-2581 (Offspring generic standard) to the sectionals, IPC-2582 through IPC-2588. A close correlation exists between this subcommittee and the Hierarchical View Product Data Description Subcommittee (2-14) in that each series identifies similar products but uses a different description methodology. The IPC-251X series looks at the product through the entire thickness while the IPC-258X series provides descriptions one layer at a time.
  • This committee is responsible for the creation, evolution, and definition of both concept definitions and standards related to machine, sensor, IT system, and cyber-physical device communications within and surrounding electronics manufacturing operations. The committee mission is to define what Industry 4.0 and ‘Industrial Internet of Things’ (IIoT) means in the context of electronics assembly, and then to define the data content and communications protocols to simplify and enable open, free, standardized support of Industry 4.0 and IIoT.
  • This committee has the responsibility for developing the format and XML characteristics for various electronic product domains. This includes material, laminate, printed board and assembly declaration profiles.
  • This task group has the responsibility of maintaining the IPC-1752 materials declaration standard. This standard defines an XML data structure to facilitate the exchange of data regarding the material content of products. This data can be used by the supply chain to assess compliance with product-related regulations such as RoHS and REACH.
  • This task group will develop a new module/section in the IPC 175x family of standards to address shipping, packing, and packaging regulatory compliance and conformance with other customer requirements. This module will not address electronic packaging as in semiconductor packaging. The new module will facilitate the gathering and exchange of information related to the compliance and conformance with customer and legal requirements pertaining to shipping, packing, and packaging materials.
  • This task group will develop a standard in the IPC 175x family that supports the electronic exchange of data needed by companies complying with regulations and customer requirements for information about conflict minerals contained within a company's products.
  • This task group will develop a standardized lab report format for gathering and communicating information on testing data for chemicals in products. This project will facilitate the exchange of lab reports between supply chain members by having a standardized lab report format and way to exchange the information contained in lab reports. The goal is to have a common format for industry to use and standardize the data so it could be entered into the data stream for easier analysis and transfer between companies within the supply chain.
  • No Description
  • This subcommittee is responsible for developing the strategy and base structure for and overseeing a series of standards for the traceability of critical parts and products used in the manufacture of printed wiring assemblies, as well as mechanical assemblies. These standards will establish minimum requirements for traceability throughout the entire supply chain. Minimum traceability requirements will be based on a new set of categories of compliance (e.g., Good, Better, Best, MIL-Standard 882-E, etc.) as identified to meet the business model/economic needs of the end-use market for the final product (telecom, aerospace, appliances, cable TV, automotive and/or consumer electronics) or a part within that product.
  • This task group is developing IPC-1782, Standard for Traceability of Critical Items Based on Risk. This standard will establish minimum requirements for traceability of items throughout the entire supply chain, with particular initial emphasis on component traceability through the manufacturing and assembly processes (e.g.; SMT, mechanical assemblies, test, etc.). Minimum traceability requirements will be based on the IPC classification system (Class 1, Class 2, Class 3) and/or another set of categories of compliance (e.g.; IPC-2610 Grades A, B, and C) based on the business model/economic needs of the end-use market for the final product (telecom, aerospace, automotive, and/or consumer electronics) or a part within that product. The standard will apply to all critical parts, components, and items as defined by the Purchaser and Supplier of equipment used in the manufacture of printed wiring assemblies, as well as mechanical assemblies. The criticality of these items will be agreed to by the purchaser and supplier through the use of this standard and MIL Standard 882-E.
  • This committee is responsible for the updating and maintenance of IPC-T-50 "Terms and Definitions for Interconnecting and Packaging of Electronic Circuits." This committee is also a feeder unit for international standardization organized in IEC 60194.
  • This committee is responsible for the development of strategies and recommendations for the conversion of design and manufacturing information into electronic formats representing final product. Various graphic drivers as well as methodologies for information capture are addressed by this committee in order to establish intelligent electronic documentation that can be communicated between design and manufacturing. This committee also includes concepts for configuration management.
  • This subcommittee is responsible for developing the concepts for capturing data electronically related to laminate, printed board, and assembly. The foundation of the work is embodied in the manufacturing profiles identified in IPC-1710, IPC-1720, and IPC-1730. Those concepts have been converted into data models and a methodology will be developed for converting the data models into XML schema.
  • This task group is a forum for discussions between IPC, UL, and the Canadian Standards Association (CSA). The group provides technical input and initiates test programs for the Recognition of materials and processes in accordance with UL and CSA standards for use in our industry.
  • This Task Group will gather data on corrosion of metals used in electronic assemblies with the intent to establish a long-term predictive test method and model. The conditions of the current 'mixed flowing gas' corrosion resistance test method are unable to predict product life and reproduce failure mechanisms in real world environments. The need for a new or modified test method is also prompted by the increasingly corrosive environments to which electronics are being subjected. NOTE: The corrosive environments to be studied by this group will focus on gaseous-based corrosion (gases, moisture vapor and particulate matter suspended in the atmosphere). Strictly solid-solid and solid-liquid contact mechanisms will not be addressed as causes of corrosion by this task group, at this time.
  • This task group is responsible for maintaining IPC-4562, "Metal Foil for Printed Wiring Applications," and is working on a new test method (TM 2.2.22) that measures the surface roughness of metal foils. The test method is measuring the roughness using non-contact techniques, providing substantially better precision and accuracy than has been available when the contact method involving a stylus is used. The surface roughness of copper foil is important to accurately know, especially when high frequencies are involved so as to better predict signal distortion or loss.
  • The objective of this task group is to determine the consistency of woven glass fabrics and their effect on laminate and prepreg manufacture and to develop meaningful performance standards. It is responsible for the maintenance of IPC-4412, "Specification for Finished Fabric Woven from 'E' Glass for Printed Boards," and IPC-SG-141, "Specification for Finished Fabric Woven from 'S' Glass for Printed Boards."
  • This roundtable task group serves as an idea-generating forum for other 3-10 Printed Base Materials Subcommittees and Task Groups that are actively involved with maintaining and developing IPC standards. The task group itself will not be responsible for generating or maintaining any documents.
  • This subcommittee is responsible for the development of technical information, guidelines and testing techniques to evaluate plating characteristics for printed boards and interconnecting substrates.
  • The Equipment Safety Subcommittee is responsible for promoting safe workplaces by encouraging good industrial practices, exchanging information on safety, and promoting realistic safety policies based on sound scientific data, and risk assessment.
  • This subcommittee serves as a clearing house for information regarding the term: "halogen-free" and its suitability for helping to describe electronic products and materials. This subcommittee has two primary focal points: 1) The maintenance and updating of the position paper, identified as IPC-WP/TR-584, IPC White Paper and Technical Report on the Use of Halogenated Flame Retardants in Printed Circuit Boards and Assemblies (Correcting the Misunderstandings on "Halogen-Free"), and 2) The leadership of any work to gather additional data and information on what can be described as halogen-free components, cables, mechanical plastics, unpopulated as well as populated printed boards and general electronic products and to then generate a guideline standard that will allow industry to keep up-to-date with this sometimes complicated and often mis-used descriptor.
  • This task group was formed to develop marking, symbols and labels for identification of lead-free and other reportable materials in lead (Pb) free assemblies, components and devices.
  • This subcommittee will document will provide documentation and training content for the processes associated with adhesive bonding in electronic assembly operations. Initial areas of consideration include (but are not limited to:) • how to decide when to use adhesives, (and when NOT to use adhesives) in electronic assembly applications • how to decide what’s needed from adhesive in a given case, • selection considerations, • surface prep, surface prep, surface prep, and the CRITICAL nature of surface prep • application considerations, • tips on checking for field degradation,etc.). Committee members from both the user community and the supplier community are actively being encouraged to participate to provide as balanced a perspective as is possible.
  • This committee provides a forum for the exchange of technical information and preparation of guidelines and standards in the following areas: - Joining techniques o Soldering requirements - Solderability testing - Soldering materials
  • This task group is developing the IPC-7070 which will replace the IPC-CM-770.
  • This task group is responsible for the development of IPC-7525, "Stencil Design Guidelines," that will assist the user in selecting stencil apertures for solder paste printing.
  • This task group is responsible for the maintenance and further development of IPC-7095, Design and Assembly Process Implementation for BGAs. This document covers the characteristics for all elements of developing a cohesive product that uses BGA packages as components in the electronic assembly. In addition, there are recommendations for void acceptability and defect analysis.
  • This task group is responsible for the maintenance and further development of IPC-7094.
  • This task group is developing IPC-7093, a companion document to IPC-7094 and IPC-7095 that describes the design and assembly challenges for implementing Bottom Termination Components (BTCs) whose external connections consist of metallized terminations that are an integral part of the component body.
  • This document covers requirements and test methods for dielectric adhesives used to hold components in place from mounting to the soldering process and for their long term properties as a part of the printed wiring board.
  • This task group is responsible for the development of a new standard intended to cover the qualifications and acceptance requirements for press-fit technology that includes the reliability needs for automotive and other industries, such as aerospace.
  • This task group is responsible for the joint industry national soldering standard, J-STD-001, and will support revision activities as necessitated by industry or technology developments.
  • This working group will be developing a new standard, parallel to the J-STD-001 which is specific to the needs of the Military procurement area. The intent of this standard is to provide the requirements with respect to soldering technologies for use in DoD contracts for the acquisition and production of military systems containing electrical and electronic assemblies. It will address any unique requirements to assure safe and reliable operations in DoD service environments. The target audience is the DoD acquisition community.
  • This Task Group is responsible for developing and maintaining an addendum to J-STD-001 to enable users to specify a standardized set of acceptance criteria unique to electronic assemblies used in the rigorous micro-gravity micro-atmosphere high mechanical stress environments associated with space electronic hardware.
  • This task group is responsible for the handbook that explains accepted industry practices for users of J-STD-001. The handbook details the process techniques, equipment, materials, and process controls needed for the production of acceptable hardware.
  • This task group is responsible for developing guidelines for thermal profiling, including thermocouple placement, and is responsible for developing a test method to standardize thermal profiling.
  • To develop a dye and press test method for components for use in IPC-1793.
  • This task group is responsible for J-STD-003, "Solderability Tests for Printed Boards," and develops new specifications on solderability test methods and related issues.
  • This task group is responsible for J-STD-002, "Solderability Tests for Component Leads, Terminations, Lugs, Terminals and Wires," and develops new specifications on solderability test methods and related issues.
  • This task group is responsible for developing and assessing revisions to J-STD-004, "Requirements for Solder Fluxes" to generate material evaluation standards that reflect current practices in all aspects of electronics assembly involving solder flux.
  • This task group is responsible for maintaining J-STD-005, "Requirements for Solder Pastes." This task group also generates standards, test methods, and a handbook that reflects current practices in all aspects of electronics manufacturing that involve solder paste.
  • This task group is responsible for the development or revisions and amendments to J-STD-006, "Requirements for Electronic Grade Solder Alloys and Fluxed and Non-Fluxed Solid Solders for Electronic Soldering Applications."
  • This task group is developing J-STD-030A, "Design, Selection and Process Implementation for Undefill Materials."
  • This committee provides a forum for the exchange of technical information and for the preparation of guidelines and standards in the following areas: - Cleaning technologies - Solvent, aqueous, semiaqueous and ultrasonic cleaning methods - Cleanliness testing and contamination control - Bare board and assembly cleanliness assessment - ROSE, SIR, HPLC and IC test methods - Solder masks - Conformal coatings
  • This subcommittee addresses issues associated with electronics cleaning. Task groups actively address cleaning materials compatibility testing, ultrasonics cleaning, and maintain cleaning handbooks compiling information on solvents cleaning, aqueous cleaning, semi-aqueous cleaning and general cleaning.
  • This task group is responsible for the maintenance of IPC-CH-65, "Guidelines for Cleaning of Printed Boards and Assemblies". Revision B was published in July, 2011.
  • This task group is responsible for the maintenance of the guideline document, IPC-7526, "Stencil and Misprinted Board Cleaning Handbook."
  • The scope is to develop a standard test method in place of Mil-Std-202 Method 215 to determine the compatibility of cleaning agents and mechanical delivery systems with general electronic assemblies, component hardware and electronic assembly materials. Currently, Mil-Std-202 and 215 test methods do not accurately represent modern cleaning chemistries and the cleaning equipment advancements that are currently used within electronic assembly manufacturing processes.
  • This task group's goals include: - Revision of 2.3.28 Ion Chromatography Test Method. - Revision of 2.3.25, ROSE test method. - Develop improved test methods for assessing cleanliness of printed wiring boards and assemblies. - Evaluate current ionic conductivity (cleanliness) acceptance limits relative to performance.
  • This task group is responsible for determining methodology and procedures for surface insulation resistance testing. Various applications are defined and provided in test methods to be included in the IPC Test Methods Manual, or specific IPC standards. This task group is responsible for IPC-9201, "Surface Insulation Resistance Handbook."
  • This task group will address the following issues: - Develop standard test methods and protocols for evaluating the residue levels on unpopulated printed wiring boards. - Develop a standard method for specifying cleanliness on bare boards using the standard test methods and protocols. - Develop a set of default cleanliness values for bare printed wiring boards. -Develop a standard test protocol to use to determine pass - fail requirements for a bare printed wiring board, other than the default values. - Develop methods for monitoring bare board cleanliness levels.
  • This task group is responsible for the determination of electrochemical migration (ECM) activity within Printed Boards. Surface ECM issues are addressed by the 5-32b SIR and Electrochemical Migration Task Group. The focus of the 5-32e Task Group is exploring Conductive Anodic Filament (CAF) growth and other ECM failure mechanisms within the board.
  • This task group is responsible for maintaining IPC-CC-830, "Qualification and Performance of Electrical Insulation Compounds for Printed Board Assemblies," (Conformal Coating) in a manner compatible with industry needs, and to assure consistency with other IPC documents. It is also responsible for maintaining compatibility with other industry criteria, especially the MIL standard.
  • This working group is developing the "UT" type coating content for inclusion into the IPC-CC-830.
  • This working group will be taking up the support of the conformal coating sections of the IPC-A-610 and J-STD-001. In addition the group will take up the topic of evaluating conformal coating for use envirionments
  • This task group is responsible for updating IPC-SM-840 "Qualification and Performance of Permanent Solder Mask." It is also responsible to maintain compatibility with other industry criteria.
  • This task group is responsible for developing IPC-HDBK-830, "Guidelines for Design, Selection and Application of Conformal Coatings." This handbook is closely related to IPC-CC-830 with focus on design, application and selection guidelines.
  • This task group will address potting and encapsulation materials, their application, and manufacturing processes. The task group will also address terminology for potting, casting, and encapsulation.
  • Low pressure molding is used throughout the electronics and automotive electronics industries. Currently there are no industry standards for design, selection, application, and acceptability criteria for LPM. In addition to the guideline document, this task group would submit acceptability criteria to the J-STD-001, IPC-A-610, and possibly the IPC-A-630 acceptability standards.
  • This subcommittee is responsible for the development maintenance of the IPC-7801 - Reflow Oven Process Control Standard.
  • Task group members are responsible for the development of test methods, a round robin test plan, carrying out the round robin program, and evaluating and reporting the round robin results for the assessment of the available test methods for accelerated testing of plated-through holes and vias (PTHs/PTVs). This task group will also be responsible for the development of guidelines for accelerated reliability testing of PTVs and guidelines for the design of reliable PTVs.
  • This task group is responsible for developing specific test and performance levels for solder attachment of surface mount devices to rigid, flexible and rigidflex circuit structures. Testing will include thermal cycling, power cycling, moisture and mechanical stress. The test methods and performance levels will be structured for specific product categories, operating environment and expected product life, based on the guidelines furnished in IPC-9701.
  • This subcommittee will develop a high-temperature printed board warpage measurement methodology focused primarily on component (land) areas. The goal is to align high-temperature printed board flatness to existing JEDEC SPP-024A (reflow flatness requirements for BGA packages) and JEDEC JESD22-B112 (high-temperature package warpage measurement methodology) which will enable a fully integrated specification for SMT optimization.
  • This subcommittee is working on IPC-2201, “Requirements for Physics of Failure Analysis for Components and Assemblies.”
  • This subcommittee is responsible for organizing all submitted test methods for preparation and inclusion in the IPC test methods manual, IPC-TM-650.
  • This subcommittee is responsible for developing concepts, guidelines, and tutorials for manual and automated microsection preparation. The prepared samples are used to evaluate the printed board and assembly quality.
  • This subcommittee is currently working on the process effects handbook for printed board assembly processes (IPC-9111). The purpose of the handbook is to provide guidance in the format of troubleshooting examples, process cause and effect information, statistical methods for correcting problems, and specific test methods related to the discovery of problem characteristics.
  • This subcommittee is currently working on the process effects handbook for printed board fabrication processes (IPC-9121). The purpose of the handbook is to provide guidance in the format of troubleshooting examples, process cause and effect information, statistical methods for correcting problems, and specific test methods related to the discovery of the problem characteristics.
  • This committee provides a forum for the exchange of technical information and for the preparation of guidelines and standards in the following areas: Automated optical inspection; Printed board acceptability; Printed board assembly acceptability; Cable and wire harness assemblies; Inspection aids; Quality assurance; Incoming inspection of raw materials; Clean rooms; Repairability
  • This subcommittee organizes the activities related to acceptability of printed board, printed board assembly products, and cable/wire harness assemblies. They foster technical discussions on printed board acceptability.
  • Charter: This task group is responsible for the updating of IPC-A-600, "Guidelines for Acceptability of Printed Boards."
  • Charter: This task group is responsible for maintaining IPC-A-610 "Acceptability of Electronic Assemblies."
  • This Task Group is responsible for developing and maintaining an addendum to IPC-A-610 to enable users to specify a standardized set of acceptance criteria unique to assemblies used in the telecom industry.
  • The IPC-A-610 Training and Certification Technical Review Committee provides industry direction and approval of the Certification Program to IPC’s standard on the Acceptability of Electronic Assemblies.
  • This task group is responsible for maintaining IPC/WHMA-A-620 "Requirements and Acceptance for Cable and Wire Harness Assemblies."
  • This Task Group is responsible for developing and maintaining an addendum to IPC/WHMA-A-620 to enable users to specifiy a standardized set of acceptance criteria unique to cable and wire harness assemblies used in the rigorous micro-gravity micro-atmosphere high mechanical stress environments associated with space electronic hardware.
  • This task group is responsible for the handbook that explains accepted industry practices for users of IPC/WHMA-A-620. The handbook details the process techniques, equipment, materials, and process controls needed for the production of cable and wire harness assemblies.
  • This task group is responsible for the development and maintenance of IPC-HDBK-630, "Guidelines for Environmental / Structural Enclosure, High Performance Applications" and IPC-A-630 "Acceptability Standard for Manufacture, Inspection and Testing of Electronic Enclosures."
  • The IPC-A-630 Training and Certification Technical Review Committee oversees the technical content of the Certification Program to IPC's standard on Accepteability for Manufacture, Inspection and Testing of Electronic Enclosures and will recommend changes as needed.
  • This task group will develop a standard to be used for the design of cable and wire harness assemblies.
  • This task group is responsible for the development and maintenance of the IPC-A-640 - Requirements and Acceptance for Fiber Optic Cable Assemblies. This standard is intended to provide information on the general design and acceptance requirements for optical fiber, optical cable and hybrid wiring harness, and installation to the extent that they can be applied to the broad spectrum of optical cable and wiring harness design. This standard will be a collection of visual, mechanical, and performance quality acceptability requirements for fiber optic cable assemblies.
  • This task group is responsible for the development of electrical continuity testing concepts and guidelines. It is also responsible for maintaining IPC-9252, "Guidelines and Requirements for Electrical Testing of Unpopulated Printed Boards."
  • This subcommittee overseas all repair and modification standards activity.
  • 8-31 TC 91: U.S. Technical Advisory Group
    This is the U.S. technical advisory group to the International Electrotechnical Commission (IEC) that deals with surface mounting and electronic assembly technology. The group develops the U.S. position to be submitted to the IEC through our U.S. National Committee (USNC).
  • 8-40 Roadmap Executive Committee
    This committee is responsible for developing the strategy for the bi-yearly production of the "IPC International Technology Roadmap for Electronic Interconnections." They coordinate the input and publication of the material provided from national and international participants in providing current, near-term, mid-term and long-term technological innovations.
  • This subcommittee is responsible for providing the input on electronic packaging, manufacturing, process development, materials, and equipment intended to describe the current state of the technology and the direction in which it is heading. The descriptions are structured to identify trends as well as paradigm shifts to guide development and preparedness for electronic equipment design through production.
  • The Lead-Free Electronics Risk Management (PERM) Council is comprised of members representing industry, Government and Academic organizations who have a common interest in managing the risks of lead-free elecrtronics in Aerospace, Defense, and High Performance (ADHP) electronics systems (e.g. Medical, Telecom, Automotive, etc.)
  • The PERM Steering subommittee is responsible for overall strategic direction and execution of the PERM Council's activities and for the long-term overall ADHP strategy and tactics to effectively deal with lead-free electronics issues. The steering subcommittee has the authority to form task groups or ad-hoc working groups and to coordinate and assign tasks resulting in actionable deliverables for the PERM Council's activities.
  • The goal of the Global Advocacy Task Group is to monitor, evaluate, and report on United States and international legislation regarding lead-free electronics so as to present a unified U.S. Aerospace, Defense and High Performance (ADHP) position to appropriate legislative groups.
  • The goal of the PERM Training Task Group is to provide the following: Provide lead-free awareness training for all U.S. DoD acquisition and technical agent organizations as well as the Defense, Aerospace and High Performance (ADHP) Industry Provide applicable training as required regarding handling, management, and implementation of lead-free technology
  • The PERM Lead-Free Processes and Controls Task Group is tasked with developing strategies and tools for controlling and managing Pb-free process and products in Aerospace, Defense and High Performance (ADHP) products as follows: Determine what Lead-Free documents and tools ADHP can use from other industries and how they can be adapted for our products Develop new Lead-Free tools and documents where ADHP’s specific needs require it
  • This task group is chartered with identifying and advocating for research programs that will address the critical needs of the Aerospace, Defense and High Performance (ADHP) industry with regard to the global transition to lead-free electronics which will include: Define, develop, and execute a systematic, coordinated plan to provide the necessary research results to address all the critical needs of the military/aerospace industry with regard to the global transition to lead-free electronics Support or provide guidance in addressing critical technical issues resulting from lead-free technology integration into high-performance electronic products (work across all PERM task teams as necessary)
  • This task group is chartered with providing the Aerospace, Defense and High Performance (ADHP) community with an efficient mechanism to disseminate information about Pb-free electronics by: Sharing information from the Aerospace & Defense Pb-free Electronics Risk Management (PERM) Council, Advisors, Committees and Working Groups : Provide conduit for wide data dissemination to the military and aerospace electronic industries Provide interface to users (conference, meeting, etc) Provide interface to military and aerospace electronic industries
  • Certain SMT component types, under certain conditions, will always have their entire tin surface converted to tin-lead - such components are termed "self-mitigating". This task group is charged with providing a statistically significant data set on self-mitigation that can be used to predict future behavior, and also with providing a basis for standardization of self-mitigation guidelines or requirements.
  • This task group is composed of members within the 8-80 PERM Council who are actively soliciting industry and U.S. DoD for funding for Pb-free Research and Development for ADHP product.
  • No Description
  • This PERM task group is chartered with evaluating current and proposed test board designs for both baseline and periodic Pb-free manufacturing process qualification. Extrapolation efforts will be taken up in follow-on task..
  • Several Aerospace, Defense and High Performance (ADHP) industry sectors requiring high reliability, including Medical and Underground Sensing for Gas and Oil, have many applications lacking suitable solutions for Pb-free assembly materials that will meet product requirements needed for high reliability over a long product lifetime. The NASA-DoD Phase 3 investigation is fundamentally different from other industry activities in that testing will be conducted that is applicable to the entire electronics industry in an unbiased, open architecture format, and will provide further understanding of bismuth containing solder alloy systems in relation to current tin/lead and SAC solder alloy soldering practices/procedures.
  • This task group was formed based on concerns raised at the Surface Mount Council regarding cracking observed in plastic chip components. They developed technical document IPC-SM-786 (Recommended Procedures for Handling of Moisture Sensitive Plastic IC Packages) to address this. Subsequently, they joined with JEDEC to develop replacements for IPC-SM-786 to reflect current technology. J-STD-020A, "Moisture/Reflow Sensitivity Classification for Plastic Integrated Circuit Surface Mount Devices," and J-STD-033, "Standard for Handling, Packing, Shipping and Use of Moisture/Reflow Sensitive Surface Mount Devices," have been published, and will be updated by this task group.
  • This subcommittee is responsible for standards for 2.5D and 3D packages, applications, processing, assembly, and design rules.
  • This subcommittee is responsible for maintaining IPC-2223, the IPC design standard for single and double-sided, multilayer and flex/rigid circuits.
  • This subcommittee is responsible for maintaining IPC-6013, the IPC performance specification for single, double-sided, multilayer flex and rigid/flex circuits.
  • This subcommittee serves as a forum for the discussion and development of new base materials for use in the manufacture of flexible PWBs. This subcommittee is responsible for the maintenance of flexible circuits base materials standards covering flexible base dielectrics (IPC-4202), adhesive-coated dielectric films (IPC-4203) and flexible metal clad dielectrics (IPC-4204).
  • This Subcommittee is responsible for generating, verifying and revising test methods which relate to all aspects (design, base materials and performance) of the D-10 Flexible Circuits Committee. All changes to existing test methods and additional test methods formulated by the D-15, Flexible Circuits Test Methods Subcommittee will be submitted to the 7-11, Test Methods Subcommittee for inclusion into the IPC-TM-650, Test Methods Manual.
  • This subcommittee is responsible for developing guidelines and specifications for products requiring high speed, high frequency, controlled impedance or microwave characteristics. The subcommittee is working to develop an IPC-2228 design standard for RF/Microwave printed boards.
  • This subcommittee is responsible for the development of IPC-6018, "Microwave End Product Board Inspection and Test."
  • This subcommittee is responsible for the development/update of IPC-4103, "Specification for Base Materials For High Speed/High Frequency Applications."
  • This task group is responsible for re-evaluating, updating, and improving the IPC-TM 650-2.5.5.7, "Characteristic Impedance and Time Delay of Lines on Printed Boards by TDR."
  • This standards group is responsible for the evaluation and completion of a new IPC Test method for obtaining Dk and Df over frequency for microwave materials (Bereskin method).
  • This task group is to determine the needs of the microelectronics industry for high-frequency dielectric test methods.
  • This task group is working on an IPC-TM-650 method for high frequency signal loss and propagation for product at 25Gbps and above.
  • This task group is responsible for the development/update of IPC-2221, "Generic Standard on Printed Board Design," and IPC-2222, "Sectional Design Standard For Rigid Organic Printed Boards."
  • This subcommittee is responsible for developing and maintaining test protocols for assessing the reliability and material/design robustness of test coupons/vehicles through the use of assembly reflow simulation profiles. The test will aid in establishing the acceptability of a printed board exposed to multiple thermal excursions in both tin-lead and lead-free processing environments.
  • This task group is responsible for the development/update of IPC-6011, "Generic Performance Specification For Printed Boards," and IPC-6012, "Qualification and Performance Specification For Rigid Printed Boards."
  • This task group is chartered with developing and maintaining an addendum to the IPC-6012, Qualification and Performance Specification for Rigid Printed Boards, that will provide specific requirements for printed boards in automotive applications.
  • This task group is chartered with developing and maintaining an addendum to the IPC-6012, Qualification and Performance Specification for Rigid Printed Boards, that will provide specific requirements for printed boards in medical device applications.
  • This task group is chartered with developing and maintaining an Addendum to the IPC-6012, Qualification and Performance Specification for Rigid Printed Boards, that addresses aerospace requirments beyond that of existing IPC-6012 Class 3 End Product requirements.
  • The IPC-6012 Training and Certification Technical Review Committee oversees the technical content of the Certification Program to the Qualification and Performance Specification for Rigid Printed Boards, and to recommend changes as needed.
  • This subcommittee is developing an IPC qualification program for the IPC-6012 rigid printed board performance specification. The program will establish a QML system that may utilize a combination of quality and/or conformance testing and existing QMS industry tools.
  • This subcommittee is responsible for developing industry guidelines on the proper handling, shipping and storage of printed boards and printed board assemblies.
  • Charter: This subcommittee is responsible for establishing and maintaining a family of process capability panel designs and standards for use by PWB suppliers and OEMs/CEMs.
  • This subcommittee is responsible for developing IPC-7092 Design and Assembly Process Implementation for Embedded Components. This document describes the design and assembly challenges for implementing passive and active components, in either formed or inserted methodology, into a printed board.
  • The D-60 Committee transitioned to a more active role in mapping and coordinating Printed Electronics standards development activities in the many D-6x subcommittees. Membership will consist of the chairs of the D-6x subcommittees and such others as they recommend as appropriate.
  • This subcommittee is responsible for generating standards related to fundamental design considerations for printed electronics. Design consideratons shall include information pertaining to material selection, layout configuration, assembly processes, test, and in service use.
  • This subcommittee is responsible for generating standards for printed electronic base materials.
  • This task group is responsible for generating standards related to additive materials applied to the surface of a substrate for printed electronics.
  • This subcommittee is responsible for generating standards related to the final printed electronics assembly. Final assemblies are considered to be functional electronic devices that are fabricated using printed electronic materials and processes.
  • This task group will define terminologies used for the base materials, design and production of printed electronics. It will cover printed electronics on flexible substrates, rigid substrates, 3D substrates and on rigid or flexible PCBs.
  • D-65 is formed as a non-publishing subcommittee/work group specifically to identify, modify as needed, create as needed, and validate (by round-robin tests and other methods as appropriate) test and measurement methods specific to printed electronics, as a shared resource for other subcommittees operating under the D-60 committee. Once validated, test methods will be proposed and submitted for inclusion through the established process for TM-650.
  • D-66 is tasked with capturing and publishing documents that support efficient and correct processing of printed electronics using materials defined in subcommittees D-61 and D-62 (and others should they be formed later) operating under the parent general committee D-60.
  • No Description
  • This subcommittee is responsible for establishing the classification system, qualification and quality conformance requirements and electrical/electronic performance requirements for electronically-integrated textiles (e-textiles).
  • This subcommittee will develop visual acceptance standards for the solar panel in final module assembly. This will include junction boxes and other attributes which would need to be inspected. For example for the junction boxes used in solar panels this would include inspection criteria for sealants and potting compounds used in the attachment. The sealants and potting compounds used could have cracking and moisture ingress so a visual inspection quality system would need to be put in place to determine acceptability which this subcommittee will help to address. • All subcommittee members • Visual Acceptance Criteria for Solar Panels - Final Module Assembly power point (presentation) • Visual Acceptance Criteria for Solar Panels - Final Module Assembly (draft standard)
  • This committee has the responsibility for developing standards to assist the electronic interconnect industry in the development of best practices and requirements for the protection of their customers intellectual property (IP) during the fabrication of printed boards for commercial, industrial, and military/high reliability markets. Currently engaged in revision of IPC-1071.
  • This committee has the responsibility for developing standards to assist the electronic interconnect industry in the development of best practices and requirements for the protection of their customers intellectual property (IP) during printed circuit assembly for commercial, industrial, and military/high reliability markets. Currently engaged in revision of IPC-1072.
  • This subcommittee, operating under the general committee E-20 Intellectual Property in the Electronics Interconnect Industry, has the responsibility for developing standards to assist the electronic interconnect industry in the development of best practices and requirements for the protection of their customers intellectual property (IP) during printed board fabrication operations for commercial, industrial, and military/high reliability markets. Closely coordinated with Validation Services audit use of IPC-107x.
  • This task group will develop a due diligence document to assist the industry in better defining due diligence for conflict minerals reporting.
  • To inform and solicit feedback from IPC's committee leaders regarding issues of importance to the organization and the industry.
  • V-SPVC Solder Products Value Council
    The Solder Products Value Council is an organization that consists of top global solder manufacturers, most of whom are top decision makers for business and technical management. The purpose of this council is to show value to the industry. This value is manifested through studies related to solder and flux chemistries, metal price market data, environmental legislation, conflict minerals, and standard review of the electronic assembly market. This council was started in 2004. Its first initiative was to eliminate the confusion of lead-free within the market place and create a standard default alloy. This study chose the SAC family of alloys, specifically selecting SAC305 as the default lead-free alloy. This resulted in industry-wide cost savings and included reducing multiply alloy inventories, providing reliability data, and eliminating perplexities within the industry.
  • The TAEC is made up of the chairmen of all IPC general committees. This committee manages IPC standardization activities. This committee provides a forum for discussions related to: IPC committee work, military specification development, technical programs for major industry seminars and technical programs conducted outside the United States.